1. Field of the Present Invention
The present invention generally relates to the field of digital circuits and more specifically to a mechanism for reducing latch counts of arbitrary L1-L2 digital circuit models to simplify verification and simulation tasks.
2. History of Related Art
While sequential digital circuits comprised of two latch sets (L1 and L2) driven by opposite phase clock signals have been well known for some time, conventional such circuits tend to include relatively simple combinational logic between the latch sets. In addition, these circuits tend to exhibit a one-to-one correspondence between latch sets such that each latch within the L1 latch set corresponded to a single L2 latch. The demand for extremely high speed and sophisticated sequential circuits, however, has resulted in a breakdown of this conventional design scheme. Combinational logic of ever increasing complexity is being placed between the L1 and L2 latch sets resulting in L1-L2 circuits lacking a simple correspondence between the latches of the L1 latch set and the latches of the L2 latch set. While these more complex circuits are required to deliver ever increasing functionality and performance, they have had a negative impact on the design cycle time, particularly in the simulation and verification phases of the design process. Simulation and verification of conventional L1-L2 circuits could be readily managed by simply collapsing the L1-L2 pairs into a single latch for modeling purposes. Halving the number of latches is highly desirable for model checking because of the exponential relationship between the number of latches and the state space of the circuit (where the circuit's state space refers to the universe of states that the circuit could conceivably occupy). In addition, because the collapsed model requires only one clock signal, verification of a particular sequence of events may be accomplished in N simulated clock transitions whereas the actual circuit would require 2N clock transitions, increased simulation capacity is achieved. Regrettably, however, because existing algorithms for collapsing L1-L2 pairs of conventional sequential circuitry depend upon a simple and direct correspondence between the L1 latches and the L2 latches, these algorithms are no longer effective in providing reduced models of arbitrary dual phase L1-L2 circuits.